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Integrated Circuit Systems, Inc.
ICS9169C-232
Frequency Generator for PentiumTM Based Systems
General Description
The ICS9169C-232 is a low-cost frequency generator designed specifically for Pentium and Pentium-Pro based chip set systems. The integrated buffer minimizes skew and provides all the clocks required. A 14.318 MHz XTAL oscillator provides the reference clock to generate standard Pentium frequencies. The CPU clock makes gradual frequency transitions without violating the PLL timing of internal microprocessor clock multipliers. A raised frequency setting of 68.5 MHz is available for Turbo-mode of the 66.8 MHz CPU. The ICS9169C-232 contains 8 CPU clocks, 6 PCI clocks, 1 REF at 48MHz and 1 at 24MHz. Either synchronous (CPU/2) or asynchronous (32 MHz) PCI bus operation can be selected by latching data on BSEL input.
Features
* * * * * * * * * * * * Strong output drive. Eight selectable CPU clocks operate up to 83.3 MHz Frequency selections include Turbo-mode speed of 68.5 MHz Maximum CPU jitter of 200ps Six BUS clocks support sync or async bus operation 250ps skew window for CPU outputs, 500ps skew window for BUS outputs CPU clocks to BUS clocks skew 1-4 ns (CPU early) 48 MHz clock for USB support & 24 MHz clock for FD. Logic inputs latched at Power-On for frequency selection saving pins as Input/Output Integrated buffer outputs drive up to 30pF loads 3.0V - 3.7V supply range, CPU (1:6) outputs 2.5V (2.375 - 2.6V) VDD option 28-pin SOIC or SSOP package
Block Diagram
Pin Configuration
28-Pin SOIC or SSOP
Functionality
3.3V10%, 0-70C Crystal (X1, X2) = 14.31818 MHz
ADD RESS SEL ECT CP U(1:8) (MHz) BU S (1:6)MHz 48MHz 24MHz RE F
FS2 FS1 0 0 0 1 1 0 0 1 1 0 0 0 1 1 1 1
FS0 0 1 0 1 0 1 0 1 50 60 66.8 75.9 55 75.9 83.3 68.5
BSEL=1 BSEL=0 25 30 33.4 32 27.5 37.5 41.7 34.25 32 32 32 32 32 32 32 32 48 48 48 48 48 48 48 48 24 24 24 24 24 24 24 24 REF REF REF REF REF REF REF REF
VDD Groups: VDD1 = X1, X2, REF/BSEL VDD2 = CPU1-6 VDD3 = CPU7-8 & PLL Core VDD4 = BUS1-6 VDD5 = 48/24 MHz
Latched Inputs: L1 = BSEL L2 = FS0 L3 = FS1 L4 = FS2
Pentium is a trademark of Intel Corporation. 9169C-232RevB031897
ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.
ICS169C-232
Pin Descriptions
PIN NUM BER PIN NAM E TYPE DESCRIPTION
1
VDD1
PWR
Power for control logic and crystal oscillator circuit and 14.318 M Hz output XTAL or external reference frequency input. This input includes XTAL load capacitance and feedback bias for a 12-16MHz crystal, nominally 14.31818M Hz. External crystal load of 30pF to GND recommended for VDD power on faster than 2.0ms. XTAL output which includes XTAL load capacitance. External crystal load of 10pF to GND recommended for VDD power on faster than 2.0ms. Ground for control logic. Processor clock outputs which are a multiple of the input reference clock as shown in the preceding table. Processor clock outputs which are a multiple of the input reference clock as shown in the preceding table. Frequency multiplier select pins. See shared pin programming description later in this data sheet for further explanation. 350K* internal pull up. Power for CPU (1:6) clock buffers only. This VDD supply can be reduced to 2.5V for CPU (1:6) outputs. Power for CPU (7:8) clock buffers and internal PLL and Core logic. Must be nominal 3.3V (3.0 to 3.7V) BUS clock outputs which are a multiple of the input reference clock as shown in the preceding table. Power for BUS clock buffers BUS (1;6) Power for fixed clock buffer (48 MHz, 24 MHz) Fixed 24 MHz clock (assuming a 14.31818 MHz REF frequency). Fixed 48 MHz clock (assuming a 14.31818 MHz REF frequency). Fixed 14.31818 M Hz clock (assuming a 14.31818 MHz REF frequency). Selection for synchronous or asynchronous bus clock operation. 350K* internal pull up.
2
X1
IN
3 4,11,16,22 6,7,9,10,15 5,12,13 5,12,13 8 14 17,18,20,21,23, 24 19 25 26 27 28
X2 GND CPU(2,3,4,5,8) CPU1, CPU6, CPU7 FS (0:2) VDD2 VDD3 BUS(1:6) VDD4 VDD5 24 MHz 48 MHz REF BSEL
OUT PWR OUT OUT IN PWR PWR OUT PWR PWR OUT OUT OUT IN
* The internal pull up will vary from 350K to 500K based on temperature
2
ICS169C-232
Shared Pin Operation Input/Output Pins
Shared Pin Operation - Input/Output, Pins 5, 28, 12 and 13 on the ICS9169C-232 serve as dual signal functions to the device. During initial power-up, they act as input pins. The logic level (voltage) that is present on these pins at this time is read and stored into a 4-bit internal data latch. At the end of Power-On reset, (see AC characteristics for timing values), the device changes the mode of operations for these pins to an output function. In this mode the pins produce the specified buffered clocks to external loads. To program (load) the internal configuration register for these pins, a resistor is connected to either the VDD (logic 1) power supply or the GND (logic 0) voltage potential. A 10 Kilohm(10K) resistor is used to provide both the solid CMOS programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. Figs. 1 and 2 show the recommended means of implementing this function. In Fig. 1 either one of the resistors is loaded onto the board (selective stuffing) to configure the device's internal logic. Figs. 2a and b provide a single resistor loading option where either solder spot tabs or a physical jumper header may be used. These figures illustrate the optimal PCB physical layout options. These configuration resistors are of such a large ohmic value that they do not effect the low impedance clock signals. The layouts have been optimized to provide as little impedance transition to the clock signal as possible, as it passes through the programming resistor pad(s).
Test Mode Operation
The ICS9169C-232 includes a production test verification mode of operation. This requires that the FS0 and FS1 pins be programmed to a logic high and the FS2 pin be programmed to a logic low(see Shared Pin Operation section). In this mode the device will output the following frequencies.
Pin Frequency
REF 48MHz 24MHz CPU (1:8) BSEL=1 BUS (1:6) BESEL = 0
REF REF/2 REF/4 REF2 REF/4 REF/3
Note: REF is the frequency of either the crystal connected between the devices X1and X2 or, in the case of a device being driven by an external reference clock, the frequency of the reference (or test) clock on the device's X1 pin.
Fig. 1
3
ICS169C-232
Fig. 2a
Fig. 2b
Fig. 3
4
ICS169C-232
Technical Pin Function Descriptions
VDD1 This is the power supply to the internal logic of the device as well as the following clock output buffers: A. REF clock output buffers B. BUS clock output buffers C. Fixed clock output buffers This pin may be operated at any voltage between 3.0 and 5.5 volts. Clocks from the listed buffers that it supplies will have a voltage swing from ground to this level. For the actual guaranteed high and low voltage levels of these clocks, please consult the AC parameter table in this data sheet. GND This is the power supply ground return pin for the internal logic of the device as well as the following clock output buffers: A. REF clock output buffers B. BUS clock output buffers C. CPU clock output buffers X1 This pin serves one of two functions. When the device is used with a crystal, X1 acts as the input pin for the reference signal that comes from the discrete crystal. When the device is driven by an external clock signal, X1 is the device' input pin for that reference clock. This pin also implements an internal crystal loading capacitor that is connected to ground. See the data tables for the value of the capacitor. X2 This pin is used only when the device uses a Crystal as the reference frequency source. In this mode of operation, X2 is an output signal that drives (or excites) the discrete crystal. This pin also implements an internal crystal loading capacitor that is connected to ground. See the data tables for the value of the capacitor. CPU (1:8) This pin is the clock output that drives processor and other CPU related circuitry that require clocks which are in tight skew tolerance with the CPU clock. The voltage swing of these clocks is controlled by that which is applied to the VDD pin of the device. See the Functionality table at the beginning of this data sheet for a list of the specific frequencies this clock operates at and the selection codes that are necessary to produce these frequencies. BUS (1:6) This pin is the clock output that is intended to drive the systems plug-in card bus. The voltage swing of these clocks is controlled by the supply that is applied to the VDD pin of the device. See the Functionality table at the beginning of this data sheet for a list of the specific frequencies that this clock operates at and the selection codes that are necessary to produce these frequencies. FS0, FS1, FS2 These pins control the frequency of the clocks at the CPU, CPUL, BUS, SDRAM, AGP and IOAPIC pins. See the Funtionality table at the beginning of this data sheet for a list of the specific frequencies that this clock operates at and the selection codes that are necessary to produce these frequencies. The device reads these pins at power-up and stores the programmed selection code in an internal data latch. (See programming section of this data sheet for configuration circuitry recommendations. BSEL When this pin is a logic 1, it will place the CPU clocks in the synchronous mode (running at half the frequency of the Ref). If this pin is a logic 0, it will be in the asynchronous mode for the CPU clocks and will operate at the preprogrammed fixed frequency rate. It is a shared pin and is programed the same way as the Frequency Select pins. VDD 2, 3 These are the power supply pins for the CPU clock buffers. By separating the clock power pins, each group can receive the appropriate power decoupling and bypassing necessary to minimize EMI and crosstalk between the individual signals. VDD2 can be reduced to 2.5V VDD for advanced processor clocks, which will bring CPU (1:6) outputs at 0 to 2.5V output swings. 48 MHz This is a fixed frequency clock that is typically used to drive Super I/O peripheral device needs. 24 MHz This is a fixed frequency clock that is typically used to drive Keyboard controller clock needs. VDD4 This power pin supplies the BUS clock buffers. REF This is a fixed frequency clock that runs at the same frequency as the input reference clock (typically 14.31818 MHz) is and typically used to drive Video and ISA BUS requirements. VDD5 This power pin supplies the 48/24 MHz clocks. 5
ICS169C-232
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0 V Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND -0.5 V to VDD +0.5 V Ambient Operating Temperature . . . . . . . . . . 0C to +70C Storage Temperature . . . . . . . . . . . . . . . . . . . . . -65C to +150C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Electrical Characteristics at 3.3V
VDD = 3.0 - 3.7 V, TA = 0 - 70 C unless otherwise stated
DC Characteristics
PARAMETER Input Low Voltage Input High Voltage Input Low Current Input High Current Output Low Current1 Output High Current
1
SYMBOL VIL VIH IIL IIH IOL IOH IOL IOH VOL VOH VOL VOH IDD
TEST CONDITIONS
MIN 0.7VDD
TYP -10.5 30.0 -38.0 25.0 -30.0 0.3 2.8 0.3 2.8 70
MAX 0.2VDD 5.0 -16.0 -14.0 0.4 0.4 140
UNITS V V A A mA mA mA mA V V V V mA
VIN = 0V VIN = VDD VOL = 0.8V; for CPU, BUS, REF CLKs VOL = 2.0V; for CPU, BUS, REF CLKs VOL = 0.8V; for fixed CLKs VOL = 2.0V; for fixed CLKs IOL = 10mA; for CPU, BUS, REF CLKs IOH = -15mA; for CPU, BUS, REF CLKs IOL = 8mA; for fixed CLKs IOH = -8mA; for fixed CLKs @66.6 MHz; all outputs unloaded
-28.0 -5.0 19.0 16.0 2.4 2.4 -
Output Low Current1 Output High Current
1
Output Low Voltage1 Output High Voltage
1
Output Low Voltage1 Output High Voltage Supply Current
1
Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production.
6
ICS169C-232
Electrical Characteristics at 3.3V
VDD = 3.0 - 3.7 V, TA = 0 - 70 C unless otherwise stated
AC Characteristics
PARAMETER Rise Time 1 Fall Time 1 Rise Time 1 Fall Time 1 Duty Cycle1 Jitter, One Sigma1 Jitter, Absolute1 Jitter, One Sigma1 Jitter, Absolute1 Input Frequency
1
SYMBOL Tr1 Tf1 Tr2 Tf2 Dt Tj1s1 Tjab1 Tj1s2 Tjab2 Fi CIN CINX ton ts Tsk1 Tsk2 Tsk3
TEST CONDITIONS 20pF load, 0.8 to 2.0V CPU & BUS 20pF load, 2.0 to 0.8V CPU & BUS 20pF load, 20% to 80% CPU & BUS 20pF load, 80% to 20% CPU & BUS 20pF load @ VOUT=1.4V CPU & BUS Clocks; Load=20pF, BSEL=1 CPU & BUS Clocks; Load=20pF, BSEL=1 REF & Fixed CLKs; Load=20pF REF & Fixed CLKs; Load=20pF
MIN 45 -250 -5 12.0
TYP 0.9 0.8 1.5 1.4 50 50 1 2 14.318 5 18 2.5 2.0 150 160 2.6
MAX 1.5 1.4 2.5 2.4 60 150 250 3 5 16.0 4.5 4.0 250 500 4
UNITS ns ns ns ns % ps ps % % MHz pF pF ms ms ps ps ns
Logic Input Capacitance1 Crystal Oscillator Capacitance1 Power-on Time 1 Frequency Settling Time 1 Clock Skew1 Clock Skew1 Clock Skew1
Logic input pins X1, X2 pins From VDD=1.6V to 1st crossing of 66.6 MHz VDD supply ramp < 40ms From 1st crossing of acquisition to < 1% settling CPU to CPU; Load=20pF; @1.4V BUS & BUS; Load=20pF; @1.4V CPU to BUS; Load=20pF; @1.4V (CPU is early)
1
Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production.
7
ICS169C-232
SSOP Package
SSOP SYMBOL
A A1 A2 B C D E e H L N
SOIC Package
MAX. 0.078 0.008 0.070 0.015 0.008 0.212 0.311 0.037 8
COMMON DIMENSIONS
MIN. 0.068 0.002 0.066 0.010 0.004 0.205 0.301 0.025 0 NOM. 0.073 0.005 0.068 0.012 0.006 See Variations 0.209 0.0256 BSC 0.307 0.030 See Variations 4
SSOP VARIATIONS
14 16 20 24 28 30
D
MIN. 0.239 0.239 0.278 0.318 0.397 0.397 NOM. 0.244 0.244 0.284 0.323 0.402 0.402 MAX. 0.249 0.249 0.289 0.328 0.407 0.407
Ordering Information
ICS9169CF-232 ICS9169CM-232
Example:
SOIC Package (wide body)
LEAD COUNT DIMENSION L 14L 0.354 16L 0.404 18L 0.454
e = 0.05 BSC
20L 24L 0.604 28L 0.704 32L 0.804
ICS XXXX F - PPP
0.504
8
ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.

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